As computer systems continue to evolve, memory systems are becoming a limiting factor on overall system performance. While the importance of memory bandwidth continues to increase, memory latency still plays a significant role in system performance. For example, at higher signaling rates, propagation delays between multiple ranks of memory devices can exceed one clock cycle, potentially resulting in different access latencies between different ranks of memory devices. Memory systems that use Direct Rambus Dynamic Random-Access Memory (RDRAM) are one example of such systems. Other memory types, such as Double Data Rate (DDR) and DDR-II employ signaling and interconnection topologies that potentially allow different ranks of DRAMs (e.g., different memory modules) to have different access latencies.
Systems using Direct RDRAMs have utilized channel levelization (hereinafter also referred to as “global levelization”) to enforce one uniform latency across all ranks of DRAMs by adding delay to those ranks of devices that can respond earlier than others. This results in increased effective bandwidth because data bubbles that exist between different ranks of DRAMs are eliminated. It also simplifies the design of the memory controller. While channel levelization provides some important benefits, it also has the negative effect of increasing DRAM latency for ranks of devices that could otherwise respond at lower latencies. As a result, in some applications there can be a loss of performance due to global levelization.